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Optima Design Automation

Sector: HPC & Semiconductors

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About Optima Design Automation

Optima Design Automation is revolutionizing automotive IC development, providing solutions to achieve ISO 26262 standard in a fraction of the time.

Products

Optima-HE; Optima-SE

The Optima Safety and Security Platform (OSSP) today consists of four overall products that provide self-contained apps for different fault analysis phases. These are driven from Optima’s core technology, the Fault Injection Engine (FIE™). Above all, the OSP dramatically improves analysis performance by orders of magnitude. This has made new analysis functions possible. That demonstrate clear adherence to the ISO 26262 standard in a fraction of the previous time. Meanwhile, also simplifying the verification process and increasing device quality. Optima’s FIE uses a different approach to fault analysis that provides the exact same data without the associated runtime overhead. In benchmarks, this solution has been proven to complete very large fault simulation runs orders of magnitude faster than the nearest competitor. This dramatically changes the dynamics of the entire Random verification process. As a result, months can be shaved off of development schedules, often at a point where time-to-market pressures are extreme. The Optima Safety and Security Platform uses the FIE to drive a series of solutions, or apps, that target specific scenarios. Optima-SA™. Static Analysis is automated to provide a clear understanding of the device faults that could prove dangerous and require analysis. Optima-HE™. Hard Error (or permanent fault) analysis is accelerated dramatically to allow for a complete analysis of a device to be performed in days rather than months for a large chip. The achieved coverage is automatically improved via Optima’s CoverageMaximizer™ technology, which identifies and provides solutions for otherwise complex problems. Optima-SE™. Soft Error (or transient fault) analysis may now be completed in a reasonable time. This app makes use of the high performance FIE to imperatively “harden” a design’s flip-flops. It is used to maximize resistance to soft errors with a minimal number of modified components, minimizing device power consumption and silicon area.

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